Pranay Harish Jain

University of Freiburg

Monday, May 18, 2026, 10:00 - 11:00

Building 102 - SR 02-012

Abstract

Three-level T-Type inverters offer reduced switching losses and improved output voltage quality compared to two-level topologies, but require active regulation of the DC-link neutral-point (NP) voltage to prevent capacitor voltage divergence that would degrade output quality and subject switching devices to unequal voltage stress.This thesis designs, implements, and comparatively evaluates four control strategies for simultaneous current tracking and NP voltage balancing in a three-level T-Type inverter with an RL load.

The main contributions revolve around applying model-based optimal control workflow to develop the control strategies. We first develop a continuous control set (CCS) model predictive control (MPC1) baseline for current tracking, whose observed NP voltage drift motivates a CCS nonlinear MPC formulation (MPC2) that embeds the full nonlinear NP voltage dynamics into the prediction model. The NP dynamics introduce a bilinear coupling through products of the phase currents and the absolute values of the modulation indices, making MPC2 a nonlinear program (NLP). We also design and implement a finite control set model predictive control (FCS-MPC) and a classical PI controller, both tailored to the T-Type topology. The optimal control problems are formulated symbolically in CasADi and solved within a MATLAB/Simulink simulation loop. We finally conduct a systematic comparative evaluation of MPC2, FCS-MPC and PI controllers under identical simulation conditions using quantitative metrics like current tracking RMSE (Root Mean Square Error), current THD (Total Harmonic Distortion), NP voltage ripple, and transient settling time.

MPC2 achieves the most balanced performance across all metrics. It maintains the tightest NP voltage regulation at both operating points (11.49 V and 22.62 V ripple before and after a reference current step, substantially below FCS-MPC and PI), produces a fast step response (0.50 ms settling time), and maintains THD of 1.06% and 1.26% before and after the step. FCS-MPC achieves the lowest post-step THD and fastest settling time but exhibits degraded NP regulation after the load step due to a structural conflict between its switching penalty and balancing objectives. PI control prevents long-term NP drift but records the highest tracking error and slowest transient response. These results validate MPC2 as an effective unified framework for three-level T-Type inverter control. Directions for future work include hardware validation, real-time solver deployment, and extension of the developed frameworks to systems with more complex load dynamics.